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Model No. | Description | iSHDSP | Standard | Features | Features |
---|---|---|---|---|---|
LR36B15 | CDS/PGA/ADC+DSP | iSHDSP: The | - | For 270-k/320-k/410-k/470-kpixel CCDs | <CDS/PGA/ADC> High-speed S/H circuit, high-gain PGA circuit, 12-bit ADC<DSP> 75-ohm video amplifier, mechanical iris control function, 10-bit DAC, synchronous signal generation circuit, CCD drive timing generator, AE control function, AWB control fun |
LR36B16 | CDS/PGA/ADC+DSP | iSHDSP: The | - | For 270-k/320-k/410-k/470-k/520-k/610-kpixel CCDs | <CDS/PGA/ADC> High-speed S/H circuit, high-gain PGA circuit, 12-bit ADC<DSP> 75-ohm video amplifier, mechanical iris control function, 10-bit DAC, synchronous signal generation circuit, CCD drive timing generator, AE control function, AWB control |
LR38653 | V driver+CDS/PGA/ADC+DSP | - | - | For 270-k/320-k/410-k/470-kpixel CCDs | <V driver> Vertical pulse driver for CCDs, 2-level output x 2, 3-level output x 2, 2-level output circuit for electronic shutter<CDS/PGA/ADC> 25 MHz, high-speed S/H circuit, high-gain PGA circuit, 12-bit ADC<DSP> 10-bit DAC, synchronous signal gene |
LR38654 | V driver+CDS/PGA/ADC+DSP | - | - | For 270-k/320-k/410-k/470-kpixel CCDs | <V driver> Vertical pulse driver for CCDs, 2-level output x 2, 3-level output x 2, 2-level output circuit for electronic shutter<CDS/PGA/ADC> 25 MHz, high-speed S/H circuit, high-gain PGA circuit, 12-bit ADC<DSP> 10-bit DAC, synchronous signal gene |